Aman Chadha • Works

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Few-shot Multimodal Multitask Multilingual Learning

iReason: Multimodal Commonsense Reasoning using Videos and Natural Language with Interpretability

iPerceive: Applying Common-Sense Reasoning to Multi-Modal Dense Video Captioning and Video Question Answering

iSeeBetter: Spatio-Temporal Video Super Resolution using Recurrent-Generative Back-Projection Networks

Git Cheatsheet

RegEx Cheatsheet

Vim Cheatsheet


Master of Science (M.S.) Thesis:
Benchmark Creation for Circuit Partitioning Algorithms

  • Gauging the performance of circuit partitioning algorithms

    We document efforts to assemble and modify a set of benchmark circuits for testing a new class of circuit partitioning algorithms designed for heterogeneous FPGAs. Often, computations can be implemented using different types of resources within these devices; the new partitioning algorithms incorporate the circuit mapping step, where computations are mapped to specific resource types, into the partitioning algorithms themselves. We elaborate on the details of this new form of partitioning, called “multi-personality” partitioning. While remapping provides a great deal of flexibility to the partitioner to modify the implementation of circuit nodes in order to meet the desired partitioning criteria, testing this new partitioner requires large, heterogeneous netlists. In this work we develop a list of requirements for the needed benchmarks, investigate existing benchmarks to determine their suitability, and document how we adapt the chosen benchmarks for use in testing multi-personality partitioning algorithms. Finally, we also discuss initial efforts in assembling and developing a set of benchmarks for testing a new form of partitioning called content-aware partitioning.

    LAMBERT Academic Publishing (Germany), ISBN-13: 978-3-659-69487-5, ISBN-10: 3659694878, EAN: 9783659694875, Pages: 72, Published on: 2015-04-15

    Buy off Amazon ($40) | Buy off MoreBooks (€36) | Book Cover | Book Table of Contents | Report | Amber Source Files and Workloads | UW-Madison Theses Repository

Parallelizing the Ocean Benchmark using Pthreads, OpenMP and MPI

  • Ocean is a simulation of large-scale sea conditions from the SPLASH benchmark suite. It is a scientific workload used for performance evaluation of parallel machines. Our version of Ocean simulates water temperatures using a large grid of integer values over a fixed number of time steps. At each time step, the value of a given grid location will be averaged with the values of its immediate north, south, east, and west neighbors to determine the value of that grid location in the next time step (total of five grid locations averaged to produce the next value for a given location). This assignment consisted of writing explicit parallel programs using two different programming styles - loop-level parallelism, shared-memory and message passing. Loop-level parallelism was exploited by starting off with the serial implementation and using an OpenMP compiler directive for parallelizing loops. The Pthreads API was used for shared-memory programming and MPI API was used for message passing.

    Serial and OpenMP Implementations | Pthreads and MPI Implementations | Download Serial and OpenMP Code | Download Pthread and MPI Code

Performing System Call Emulation and Full System Simulation using the gem5 Architectural Simulator

  • This assignment consisted of setting up gem5, performing Syscall Emulation (SE), Full System (FS) Simulation, and simulating programs to observe speedup trends using SE and FS modes.

    Project Report | Download Code

Decoupled Compressed Caches for GPUs

  • With increase in the power consumption of computing systems, focus has shifted towards techniques that can improve the effective resource utilization. Cache Compression is one such technique that increases the effective cache capacity and thereby improving the performance of the system. In the current paper, we evaluate cache compression for GPUs. We analyze the suitability of compression to GPU workloads by implementing a Decoupled Compressed Cache as the Last Level Cache. We simulated the design in GPGPU-Sim and evaluated the design for a set of integer and floating-point benchmarks. We observed a 1-3% improvement in the cache miss rate for most of the benchmarks.

    Project PPT | Project Report | Project Script(s)

Patch Study on the Linux Kernel Memory Module

  • We perform a detailed analysis and classification of patches applied to Linux Kernel focussing particularly on patches related to memory module. After analysis and classification of patches related to the memory module of Linux Kernel versions 2 and 3, we observe the pattern of mistakes leading to necessity of kernel patches. We then identify the distribution of multiple patches attempting to fix same bug which we call as fix-fixes. Through our observations, we put together a short guideline of programming practices to avoid most frequent mistakes we encountered.

    Project PPT | Project Report | Patch Analysis Data | Project Script(s)

Linux Infokernel: Implementation and Extension

  • The infokernel, proposed by Arpaci-Dusseau et al., allows operating systems to be used in a more flexible and appropriate manner by higher-level services. It exposes key pieces of information about its algorithms and internal state; thus, its default policies become mechanisms, which can be controlled from user-level. In this project, we develop an Informed Virtual Memory system that exposes which physical pages various virtual pages are mapped to. We also develop an Informed File System which takes an offset in a given (previously opened) file and, if successful, returns back the disk block that the file resides in. We develop a test-case suite which validates functionality of both the Informed Virtual Memory system and the Informed File System. We then propose a system call that exposes the limit of virtual memory pages available for current process. Such a system call can be useful in a scenario in which a program may have to perform operations on a certain data set. For instance, if the program seeks to sort the data set, then at that point in the program, it may dynamically choose to implement a particular sorting algorithm based on its space complexity and the current available virtual memory page limit.

    Video Tutorial | Source Files | Project Readme

AFS and NFS: A Comparative Study

  • An implementation of a set of programs that outperform NFS in comparison to AFS, and vice-versa. We also studied the properties of each system being exploited in this comparison.

    Programs | Project Readme

Linux Kernel Building and Hacking

  • In this warm-up OS project, we build the linux kernel, get it to run in a virtualized environment and modify it by adding some counters into the Linux ext2 file system code. We then add a system call to return the value of that counter.

    Video Tutorial | Source Files | Project Readme

Eraser: A Dynamic Data Race Detector for Multi-Threaded Programs

Adaptive Replacement Cache

  • An implementation of the Adaptive Replacement Cache, a page replacement algorithm which offers better performance than the Least Recently Used replacement algorithm by keeping track of both frequently-used and recently-used pages coupled with a recent eviction history for both.

    Source and Trace files

Components of Operating Systems

  • Command Line Interpreter (Shell)
    Designed a command line interpreter which could handle sequential commands, background commands, output redirection and batch mode.

    Project Description | Download Source

    Virtual Memory
    A demand paged virtual memory model was implemented with a random policy, FIFO and 2FIFO as page-replacement algorithms. In addition, a custom algorithm intended for flash drives, which offered lesser disk reads and writes while still offering the least page faults, was devised.

    Project Description | Download Source | Download Report | Download Detailed Result Analysis

    RAID Manager
    A software-based RAID manager was implemented with failure-handling and data recovery capability for RAID 0, RAID 1, RAID 4, RAID 5 and RAID 10.

    Project Description | Download Source

    Thread Synchronization
    A search engine was implemented which consisted of a file system scanner that reads in file names; an indexer that adds all the words in a file to a hash table; and a search interface that allows you to type in a word and get back a list of files containing the word. Each of these components ran concurrently as a separate thread.

    Project Description | Download Source

Dynamic Cache Resizing and Frequency Scaling using Machine Learning

  • Designed a system using gem5 which adapts to changes in workload characteristics using a Machine Learning algorithm and accordingly performs Cache Resizing and Dynamic Frequency Scaling (DFS) to improve the power efficiency of the system.

    Project Presentation | Project Report

Verilog HDL Parser

  • Designed a parser for the Verilog 2001 standard in C that could parse a Verilog HDL file into an intermediate representation format having module names and their connections.

    Features include:
    • Support for connect-by-name and connect-by-reference type of connections.
    • Concatenation of consecutive lines until a complete module instantiation is formed. This feature was particularly intended for netlists obtained from Synposys Design Compiler.
    • Support for disambiguation between a bus referenced with its entire range (without an [X:Y]) from a bus referenced with an [X:Y] in its name.
    • Ability to split up the bus when you have an [X:Y] in the bus name so each signal of the bus can be identified.
    • Support for parsing of Escaped identifiers: \XYZ/abc or \abc.
    • Ability to output a catalogue at the end of parsing with a list of unique modules and a count of the # of instantiations of each module.

    Project Readme | Source | Sample Circuits

Design of a 5-Stage Pipelined Processor

  • A complete functional design of a 16-Bit Microprocessor was implemented in this project. Designed components include an ALU, Instruction Decoder, Data Memory, Instruction Memory and a Register File (with a Data Segment register for Load/Store instructions and a Stack Pointer register for Call/Return instructions).

    Features include:
    • ISA can be found here
    • Data Forwarding Unit (to forward data from the EX and MEM stages)
    • Hazard Detection Unit (to handle Load-Use Hazards)
    • Branch Control Unit (to handle 8 different branch conditions)
    • Stall and Flush functionality
    • A Flag Register with three flags: Zero (Z), Overflow (V), and Sign bit (N)

    Verification of the entire system was carried out by considering corner cases. The project was initially developed as a single-cycle datapath implementation and later extended to a 5-stage pipelined design.

    Screenshots for the single-cycle implementation | Screenshots for the 5 stage pipeline implementation | Project Description | Project Report | Project Presentation

High Speed Calibratable Angle Resolver using Verilog

  • A high speed, high precision angle resolver was designed. It had a 2-channel 12-bit A2D converter to sample a sine and cosine signal from an angle sensor. The sine channel generated an output that is A*sin(a)+B, and the cosine channel generated C*cos(a)+D. The B and D terms represent undesired offsets that have to be cancelled through calibration. A and C represent unknown scaling terms that also need normalization through calibration. Calibration coefficients were stored in the EEPROM. After each channel is digitally corrected for offset and gain, the angle was calculated by the digital core, and available on the SPI interface.
    Possible applications of this module include being a part of a power steering angular sensor or a Variable-frequency drive system for an AC motor.

    Chip Block Diagram | Project Description

Bachelor of Engineering (B.E.) Dissertation:
Smart and Energy-Efficient Home Automation using Gesture Recognition

Biometric Database Protection using Public Key Cryptography

  • Advisor: Prof. M. Mani Roja, Thadomal Shahani Engineering College

    With the increasing need for stringent security measures in recent times, biometric systems have assumed greater importance for information security systems. For biometric systems to offer reliable security, they themselves have to satisfy high security requirements to ensure invulnerability. Two different approaches based on RSA and Elliptic Curve Cryptography for database protection of biometric authentication systems, were investigated via this project. Current database protection schemes and image encryption schemes were explored. Implementations of public key algorithms has been realized for experimental purposes and the results thus obtained, have been critically analyzed.

Portable Patient Monitoring System

  • Advisor: Prof. Y. S. Rao, Sardar Patel Institute of Technology

    An integrated system that aims at providing patient identification, monitoring of abnormal body conditions, tracking, rescue and response to deal with life-threatening emergencies. The project involves processing of body signals and monitoring of body weight, blood pressure and pulse oximetry to identify critical body conditions and generate alert triggers that could be transmitted to a monitoring station in case of an abnormality. A Bluetooth interface would enable the system to communicate to an application end-point in a mobile handset which can forward the data through GPRS or a GSM channel. As part of the research team, my role in this project is to accomplish the processing of body signals such as ECG, to aid the detection and diagnosis of cardiac abnormalities. In this project, we have utilized the MIT-BIH ECG Database. MATLAB simulations of QRS detection in the ECG were been carried out and the algorithm was ported to the ARM7 based system. The project is sponsored by the Innovation and Entrepreneurship Development Centre (IEDC) under Government of India, with a grant of Rs. 60,000.

    Download (QRS Detection MATLAB Codes) | QRS Detection Initial Plan of Action | QRS Detection Final Outcome and Results | QRS Detection and Extraction Papers (Copyright with original authors and IEEE) | Project Aim and Proposal

RF Mobility, an RFID based 'Track-n-Trace' project

  • Advisor: Rajeev Pradhan, Vice President – Information Technology, Arshiya International Ltd.

    The project included a Java-based interface for guiding various industrial logistics functions such as Cycle Count, Inventory Tracking, Palletization, Unloading etc. and supported 7 types of barcode reading namely UPC-E, EAN-8, EAN-13, Code 128, Interleaved 2 of 5, Code 39 and QR Code. The project was sponsored by Arshiya International, a supply chain and logistics infrastructure company.

    Download (Executable) | Screenshots | Download (Source) | Barcode Samples | Extended Description

Biometric authentication using signature verification by a novel cascaded algorithmic approach

  • Advisor: Prof. M. Mani Roja, Thadomal Shahani Engineering College

    This project aimed at developing a signature-based authentication system using a novel cascaded algorithmic approach. The system delivered exceptional accuracy rates and excellent time-response.

Algorithms for Embedded Computer Vision Systems

  • Advisor: Prof. Y. S. Rao, Sardar Patel Institute of Technology

    The primary goal was to perform image processing algorithms on an embedded board comprising of a microcontroller chip subtracting out any kind of computer interface.

Real-Time American Sign Language (ASL) Recognition

  • The main aim of this project was to develop a system for recognizing sentence-level continuous American Sign Language (ASL) using a desk mounted camera by tracking the user's hand movements.

Handwritten Character Recognition using Neural Networks

  • A multi-layered neural network based algorithm was employed, and a six element feature vector was used which was found to be reliable in identifying all characters on a standard QWERTY keyboard. A MATLAB GUI enabled the user to either train or test the network on a ‘one character at a time’ basis.

CMOS Camera C3088 interface for Atmel AVR ATmega16 Microcontroller

  • An interface between a CMOS camera and a computer using the AVR microcontroller was designed. The interface allowed the user to fetch images from the camera as well as to change some of the properties of the camera such as brightness, luminance, etc.

Object Tracking using Image Warping and Kalman Filtering

  • Involved a segmentation-based method of object tracking using image warping and Kalman filtering. Head and hand tracking were performed using this method to demonstrate its performance.

Digital Watermarking

  • Image in image, image in video and video in video watermarking was implemented using the Discrete Wavelet Transform and the Discrete Cosine Transform with a focus on invisibility and recoverability.

Design, Development and Implementation of FIR, IIR and Adaptive Filters

  • Under this project, filters of different specifications were developed using FIR, IIR and Adaptive algorithms, such as Least Mean Squares (LMS). The C codes were implemented on the TMS320C6713 Floating-Point Digital Signal Processor from Texas Instruments and satisfactory results were achieved.

Text-Independent Speaker Recognition using Mel‐Cepstrum

  • Fundamental frequency estimation, i.e., pitch detection, was performed using Mel Frequency Cepstral Coefficients (MFCCs) and vector quantization was used to minimize the amount of data to be handled.

Digital Temperature Sensor

  • Conceptualized and designed a temperature sensing and displaying unit using the LM35D precision centigrade temperature sensor and AVR microcontroller.

Project based on the event ‘Roll Of Die’ using Image Processing Algorithms

  • Developed a system to detect the number appearing on the die using image processing techniques with the help of an overhead camera.

Fire-fighting Robot

  • Developed a Robotic system consisting of an AVR microcontroller, digital IR sensors and motors which when kept in a grid, could detect fire, go towards it and extinguish the fire.

Mini Projects

Web Design Projects

Presentation and Report: Maglev Trains

Presentation and Report: International Trade

Presentation: IPTV

Presentation: Urban Green Ideas

  • The presentation talked about using the latest technology to overcome and minimize effects of congestion and overpopulation in metropolitan cities like Mumbai. Credits to Divya Jyoti for the awesome PPT.

    Download (PDF) | Download (PPT)

Presentation: Linux v/s Windows

Presentation: PCT Proposal

  • As part of my undergrad engineering curriculum, my team developed a proposal for the renovation of the gymkhana and the entertainment room (we seriously needed it!)

    Download (PDF) | Download (PPT)

Presentation: Basics of Web Designing Workshop

  • I took this presentation with Divya Jyoti, my colleague, on Web Designing (basics) for CSI-TSEC which covered HTML and CSS. We intended to take elementary PHP too, but time left us no choice but to drop the idea!

    Download (PDF) | Download (PPT)

Presentation: MATLAB Workshop

Presentation: North America Presentation

Presentation: Fiber Optic Cables

  • Introduction to optical fiber communication, classification of FOC based on modes (single mode, multi mode), linearly polarized model.

    Download (PDF) | Download (PPT)

Presentation: Web-Based Home Appliances Controlling System

  • A presentation we made for a competition "Enquest 2012", an inter-collegiate techno-commercial competition. The competition was basically for a commercial-product idea that involved a good degree of practical feasibility.

    Download (PDF) | Download (PPT)

Workshop Flyers: PC Assembling, Linux and Windows 7

Miscellaneous Downloads