Verilog HDL Parser
   

Authors: Aman Chadha, Tony Gregerson, Katherine Morrow 
Department of Electrical and Computer Engineering
University of Wisconsin-Madison



Features:

- Supports connect-by-name and connect-by-reference type of connections.

- Concatenates consecutive lines until a complete module instantiation is formed. Feature intended for netlists obtained from Synposys Design Compiler.

- Supports disambiguation between a bus referenced with its entire range (without an [X:Y]) from a bus referenced with an [X:Y] in its name.

- Splits up the bus when you have an [X:Y] in the bus name so each signal of the bus can be identified.

- Supports parsing of Escaped identifiers: \XYZ/abc or \abc.

- Outputs a catalogue at the end with a list of unique modules and a count of the # of instantiations of each module.